Verified Commit 0d37c6dc authored by Javinator9889's avatar Javinator9889 🎼

Updated code with comments

parent 25ceaef6
-- Eric Bainville
-- Mar 2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
......
library work;
use work.UTILITIES.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bitStringController is
port (
bitString: in std_logic_vector (7 downto 0);
bitString: in std_logic_vector (7 downto 0); -- Received data
motor: out std_logic_vector (5 downto 0);
movement: out std_logic;
pulses: out integer
motor: out std_logic_vector (5 downto 0); -- Selected motor
movement: out std_logic; -- Direcction
pulses: out std_logic_vector (6 downto 0) -- Degrees
);
end bitStringController;
architecture behavioral of bitStringController is
begin
signal codeMotor: std_logic_vector (2 downto 0)
signal codeMove: std_logic_vector (1 downto 0)
signal enableVector: std_logic_vector ( 5 downto 0);
signal codeMoveToPulses: integer;
signal direction: std_logic;
-- Signals related with the relevant bits
signal codeMotor: std_logic_vector (2 downto 0);
signal codeMove: std_logic_vector (1 downto 0);
bitController: process(bitString)
begin
codeMotor <= get_motor_from_binary_code(bitString);
codeMove <= get_movement_from_binary_code(bitString);
case codeMotor is
when "000" => enableVector <= "000001";
when "001" => enableVector <= "000010";
when "010" => enableVector <= "000100";
when "011" => enableVector <= "001000";
when "100" => enableVector <= "010000";
when "101" => enableVector <= "100000";
when others => enableVector <= "000000";
end case;
case codeMove is
when "00" => direction <= '0'; codeMoveToPulses <= '50';
when "01" => direction <= '1'; codeMoveToPulses <= '50';
when "10" => direction <= '0'; codeMoveToPulses <= '100';
when "11" => direction <= '1'; codeMoveToPulses <= '100';
end case;
motor <= enableVector;
movement <= direction;
pulses <= codeMoveToPulses;
-- Covered in documentation
bitStringControl : process(bitString)
begin
codeMotor(0) <= bitString(0);
codeMotor(1) <= bitString(1);
codeMotor(2) <= bitString(2);
codeMove(0) <= bitString(3);
codeMove(1) <= bitString(4);
end process;
-- Covered in documentation
cMotorProcess: process(codeMotor)
begin
case codeMotor is
when "000" => motor <= "000001";
when "001" => motor <= "000010";
when "010" => motor <= "000100";
when "011" => motor <= "001000";
when "100" => motor <= "010000";
when "101" => motor <= "100000";
when others => motor <= "000000";
end case;
end process;
-- Covered in documentation
cMoveProcess: process(codeMove)
begin
case codeMove is
when "00" => movement <= '0'; pulses <= "0110010";
when "01" => movement <= '1'; pulses <= "0110010";
when "10" => movement <= '0'; pulses <= "1100100";
when "11" => movement <= '1'; pulses <= "1100100";
when others => movement <= '0'; pulses <= "0000000";
end case;
end process;
-- Covered in documentation
cPulsesProcess: process(codeMove)
begin
case codeMove is
when "00" => pulses <= "0110010";
when "01" => pulses <= "0110010";
when "10" => pulses <= "1100100";
when "11" => pulses <= "1100100";
when others => pulses <= "0000000";
end case;
end process;
end behavioral;
......
#JA PINS
set_property PACKAGE_PIN J1 [get_ports {clockOut}]
set_property IOSTANDARD LVCMOS33 [get_ports {clockOut}]
set_property PACKAGE_PIN L2 [get_ports {dirOut}]
set_property PACKAGE_PIN J1 [get_ports {clkOut}] #Motor clock
set_property IOSTANDARD LVCMOS33 [get_ports {clkOut}]
set_property PACKAGE_PIN L2 [get_ports {dirOut}] #Direction
set_property IOSTANDARD LVCMOS33 [get_ports {dirOut}]
set_property PACKAGE_PIN J2 [get_ports {enableOut}]
set_property IOSTANDARD LVCMOS33 [get_ports {enableOut}]
set_property PACKAGE_PIN J2 [get_ports {enableMotor[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {enableMotor[0]}]
set_property PACKAGE_PIN G2 [get_ports {enableMotor[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {enableMotor[1]}]
set_property PACKAGE_PIN H1 [get_ports {enableMotor[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {enableMotor[2]}]
set_property PACKAGE_PIN K2 [get_ports {enableMotor[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {enableMotor[3]}]
set_property PACKAGE_PIN H2 [get_ports {enableMotor[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {enableMotor[4]}]
set_property PACKAGE_PIN G3 [get_ports {enableMotor[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {enableMotor[5]}]
# ledOutVectors
set_property PACKAGE_PIN U16 [get_ports {ledOutVector[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ledOutVector[0]}]
set_property PACKAGE_PIN E19 [get_ports {ledOutVector[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ledOutVector[1]}]
set_property PACKAGE_PIN U19 [get_ports {ledOutVector[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ledOutVector[2]}]
set_property PACKAGE_PIN V19 [get_ports {ledOutVector[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ledOutVector[3]}]
set_property PACKAGE_PIN W18 [get_ports {ledOutVector[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ledOutVector[4]}]
set_property PACKAGE_PIN U15 [get_ports {ledOutVector[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ledOutVector[5]}]
set_property PACKAGE_PIN U14 [get_ports {ledOutVector[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ledOutVector[6]}]
set_property PACKAGE_PIN V14 [get_ports {ledOutVector[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ledOutVector[7]}]
#SYS_CLOCK
set_property PACKAGE_PIN W5 [get_ports clk]
set_property PACKAGE_PIN W5 [get_ports clk] #100 MHz Oscillator on port W5
set_property IOSTANDARD LVCMOS33 [get_ports clk]
#switch
set_property PACKAGE_PIN V17 [get_ports {dir}]
set_property IOSTANDARD LVCMOS33 [get_ports {dir}]
set_property PACKAGE_PIN V16 [get_ports {enable}]
set_property IOSTANDARD LVCMOS33 [get_ports {enable}]
\ No newline at end of file
#UART PINS
set_property PACKAGE_PIN B18 [get_ports uart_rx_pin]
set_property IOSTANDARD LVCMOS33 [get_ports uart_rx_pin]
set_property PACKAGE_PIN A18 [get_ports uart_tx_pin]
set_property IOSTANDARD LVCMOS33 [get_ports uart_tx_pin]
\ No newline at end of file
-- EB Mar 2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
std_logic
entity t_serial is
port(
sys_clk: in std_logic; -- 100 MHz system clock
......@@ -115,5 +114,4 @@ begin
end process;
end Behavioral;
end Behavioral;
\ No newline at end of file
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity motorOrchestrator is
port (
clk: in std_logic;
nPulses: in integer;
enableIn: in std_logic_vector (5 downto 0);
dirIn: in std_logic;
dirOut: out std_logic;
enableOutVector: out std_logic_vector (5 downto 0);
clkOut: out std_logic
generic(
init_val: std_logic := '0'
);
port (
clk: in std_logic; -- Divided clock
nPulses: in std_logic_vector (6 downto 0); -- Degrees (bit)
enableIn: in std_logic_vector (5 downto 0); -- Selected motor (bit)
dirIn: in std_logic; -- Direction (bit)
pulsesFinishedIn: in std_logic := init_val; -- Aux signal FSM
pulsesFinishedOut: out std_logic := init_val; -- Aux signal FSM
dirOut: out std_logic; -- Output signal (direction)
enableOut: out std_logic_vector (5 downto 0) -- Output signal (selected motor)
);
end motorOrchestrator;
architecture behavioral of motorOrchestrator is
signal counter : integer := 0;
-- Signal to control pulses of the motor
signal counter : std_logic_vector (6 downto 0) := (others => '0');
-- Inversed logic in enable module A4988
component stepperMotor is
port (
enable: in std_logic;
......@@ -26,38 +33,38 @@ architecture behavioral of motorOrchestrator is
end component;
begin
m0: stepperMotor port map( enable => enableOutVector(0) );
m1: stepperMotor port map( enable => enableOutVector(1) );
m2: stepperMotor port map( enable => enableOutVector(2) );
m3: stepperMotor port map( enable => enableOutVector(3) );
m4: stepperMotor port map( enable => enableOutVector(4) );
m5: stepperMotor port map( enable => enableOutVector(5) );
STEP : process (clk)
-- Motor components needed
m0: stepperMotor port map ( enable => enableIn(0),
enableOut => enableOut(0));
m1: stepperMotor port map ( enable => enableIn(1),
enableOut => enableOut(1));
m2: stepperMotor port map ( enable => enableIn(2),
enableOut => enableOut(2));
m3: stepperMotor port map ( enable => enableIn(3),
enableOut => enableOut(3));
m4: stepperMotor port map ( enable => enableIn(4),
enableOut => enableOut(4));
m5: stepperMotor port map ( enable => enableIn(5),
enableOut => enableOut(5));
-- Process to check how many pulses have been done
nSTEP : process (clk)
begin
if clk'event and clk='1' then
if enableIn /= (others => 0) then
if counter < nPulses then
counter = counter + 1;
else
counter <= 0;
enableIn <= (others => 0);
end if;
if counter <= nPulses and pulsesFinishedIn='0' then
counter <= counter + 1;
pulsesFinishedOut <= '0';
else
counter <= (others => '0');
pulsesFinishedOut <= '1';
end if;
end if;
end process;
ENABLE : process (enableIn)
begin
enableOutVector <= enableIn;
end process;
-- Process to assist the direction output
DIRECTION : process (dirIn)
begin
dirOut <= dirIn;
end process;
end behavioral ; -- behavioral
end behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity orchestrator is
port (
clk: in std_logic;
clk: in std_logic; -- Oscillator Pin
uart_rx_pin: in std_logic; -- RX Pin
uart_tx_pin: out std_logic; -- TX Pin
uart_rx: in std_logic;
uart_tx: out std_logic
dirOut: out std_logic;
enableOutVector: out std_logic_vector (5 downto 0);
clkOut: out std_logic; -- Motor Clock output
dirOut: out std_logic; -- Motor direction output
enableMotor: out std_logic_vector(5 downto 0); -- Motor enabled vector
ledOutVector: out std_logic_vector (7 downto 0) -- LEDs Pin
);
end orchestrator;
architecture behavioral of orchestrator is
-- Signals for dividing the clock
signal dividedClkEvent: std_logic := '0';
signal counter: std_logic_vector (17 downto 0) := (others => '0');
-- Signals for receiving input data from USB
signal sys_clk: std_logic;
signal data: std_logic_vector (7 downto 0);
signal dataMotor: std_logic_vector (7 downto 0);
-- Signals for parsing the input data
signal motor_number: std_logic_vector (5 downto 0);
signal movement: std_logic;
signal pulses: std_logic_vector (6 downto 0);
-- Signal for active wait on motors
signal pulsesFinishedIn: std_logic := '0';
signal pulsesFinishedOut: std_logic := '0';
-- Signal for changed data
signal hasChanged: std_logic;
-- FSM to accomplish the casuistic covered in the documentation
type stateType is (A, B);
signal state_reg: stateType := B;
signal state_next: stateType;
component t_serial is
port (
sys_clk: in std_logic;
data: out std_logic_vector (7 downto 0);
uart_rx: in std_logic;
sys_clk: in std_logic; -- Oscillator
uart_rx: in std_logic; -- RX PIN
led: out std_logic_vector (7 downto 0); -- Data
uart_tx: out std_logic
);
end component;
component bitStringController is
port (
bitString: in std_logic_vector (7 downto 0);
bitString: in std_logic_vector (7 downto 0); -- Data
motor: out std_logic_vector (5 downto 0);
movement: out std_logic;
pulses: out integer;
)
motor: out std_logic_vector (5 downto 0); -- Motor enabled vector
movement: out std_logic; -- Motor Direction
pulses: out std_logic_vector (6 downto 0) -- Motor degrees
);
end component;
component motorOrchestrator is
port (
clk: in std_logic;
nPulses: in integer;
enableIn: in std_logic_vector (5 downto 0);
dirIn: in std_logic;
dirOut: out std_logic;
enableOutVector: out std_logic_vector (5 downto 0);
clkOut: out std_logic;
)
clk: in std_logic; -- Motor clock
nPulses: in std_logic_vector (6 downto 0); -- Motor degrees (input data)
enableIn: in std_logic_vector (5 downto 0); -- Motor enabled vector (input data)
dirIn: in std_logic; -- Motor direction (input data)
pulsesFinishedIn: in std_logic; -- AUX Signal
pulsesFinishedOut: out std_logic; -- AUX Signal
dirOut: out std_logic; -- Direction out
enableOut: out std_logic_vector (5 downto 0) -- Motor enabled vector (out data)
);
end component;
-- Signals for dividing the clock
signal counter: std_logic_vector (17 downto 0) := (others => '0');
signal dividedClkEvent: std_logic := '0';
-- Signals for receiving input data from USB
signal sys_clk: std_logic;
signal data: std_logic_vector (7 downto 0);
signal uart_rx: std_logic;
signal uart_tx: std_logic;
-- Signals for parsing the input data
signal bit_string: std_logic_vector (7 downto 0);
signal motor_number: std_logic_vector (5 downto 0);
signal movement: std_logic;
signal pulses: integer;
begin
serial: t_serial port map (sys_clk, data, uart_rx, uart_tx);
bit_controller: bitStringController port map (bit_string, motor_number, movement, pulses);
motor_handler: motorOrchestrator port map (clk => clkOut,
serial: t_serial port map (sys_clk => clk,
led => data,
uart_rx => uart_rx_pin,
uart_tx => uart_tx_pin);
bit_controller: bitStringController port map (bitString => dataMotor,
motor => motor_number,
movement => movement,
pulses => pulses);
motor_handler: motorOrchestrator port map (clk => dividedClkEvent,
nPulses => pulses,
enableIn => motor_number,
dirIn => movement,
pulsesFinishedIn => pulsesFinishedIn,
pulsesFinishedOut => pulsesFinishedOut,
dirOut => dirOut,
enableOutVector => enableOutVector,
clkOut => clkOut);
enableOut => enableMotor);
-- Process to create the divided clock from the oscillator
CLK_DIVIDER: process(clk)
begin
if (clk'event and clk = '1') then
......@@ -85,12 +112,51 @@ begin
end if;
end if;
clkOut <= dividedClkEvent;
sys_clk <= clk;
end process CLK_DIVIDER;
MANAGE_DATA: process(data)
-- Received new data
AUX_EVENT: process(dividedClkEvent)
variable newdata: std_logic_vector(7 downto 0) := "11110000";
begin
bit_string <= data;
end process MANAGE_DATA;
if (data /= newdata) then
hasChanged <= '1';
newdata := data;
else
hasChanged <= '0';
end if;
end process;
-- FSM RESET to default
FSM_RESET_ASYNC: process(dividedClkEvent, hasChanged)
begin
if hasChanged = '1' then
state_reg <= A;
elsif falling_edge(dividedClkEvent) then
state_reg <= state_next;
end if;
end process;
-- FSM transitions
FSM_ACT: process(pulsesFinishedOut, hasChanged, state_reg)
begin
ledOutVector <= data;
state_next <= state_reg;
pulsesFinishedIn <= '0';
dataMotor <= data;
case state_reg is
when A =>
if pulsesFinishedOut = '0' then
pulsesFinishedIn <= '0';
dataMotor <= data;
state_next <= B;
end if;
when B =>
if pulsesFinishedOut = '1' then
pulsesFinishedIn <= '1';
dataMotor <= "11111111";
state_next <= B;
end if;
end case;
end process;
end architecture behavioral;
\ No newline at end of file
......@@ -4,9 +4,9 @@ use ieee.std_logic_unsigned.all;
entity stepperMotor is
port (
enable: in std_logic;
enable: in std_logic; -- Enable data
enableOut: out std_logic
enableOut: out std_logic -- Enable out signal
);
end entity stepperMotor;
......@@ -14,6 +14,7 @@ architecture behavioral of stepperMotor is
begin
-- Process to reverse the logic for the A4988 module
ENB : process (enable)
begin
if(enable='1') then
......
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