Verified Commit 0fa4b45e authored by Javinator9889's avatar Javinator9889 🎼

Almost completed orchestrator

parent 6d035109
......@@ -2,7 +2,7 @@
library IEEE;
entity t_serial is
sys_clk: in std_logic; -- 100 MHz system clock
library IEEE;
entity orchestrator is
port (
clk: in std_logic;
clkOut: out std_logic
end orchestrator;
architecture behavioral of orchestrator is
component t_serial is
port (
sys_clk: in std_logic;
data: out std_logic_vector (7 downto 0);
uart_rx: in std_logic;
uart_tx: out std_logic
end component;
component bitStringController is
port (
bitString: in std_logic_vector (7 downto 0);
motor: out std_logic_vector (2 downto 0);
movement: out std_logic;
pulses: out integer;
end component;
component motorOrchestrator is
port (
clk: in std_logic;
nPulses: in integer;
enableIn: in std_logic_vector (5 downto 0);
dirIn: in std_logic;
dirOut: out std_logic;
enableOutVector: out std_logic_vector (5 downto 0);
clkOut: out std_logic;
end component;
-- Signals for dividing the clock
signal counter: std_logic_vector (17 downto 0) := (others => '0');
signal dividedClkEvent: std_logic := '0';
-- Signals for receiving input data from USB
signal sys_clk: std_logic;
signal data: std_logic_vector (7 downto 0);
signal uart_rx: std_logic;
signal uart_tx: std_logic;
-- Signals for parsing the input data
signal bit_string: std_logic_vector (7 downto 0);
signal motor_number: std_logic_vector (2 downto 0);
signal movement: std_logic;
signal pulses: integer;
-- Signals for managing the motors
serial: t_serial port map (sys_clk, data, uart_rx, uart_tx);
CLK_DIVIDER: process(clk)
if (clk'event and clk = '1') then
counter <= counter + 1;
if (counter = "11000011010100000") then
dividedClkEvent <= not dividedClkEvent;
counter <= (others => '0');
end if;
end if;
clkOut <= dividedClkEvent;
sys_clk <= clk;
end process CLK_DIVIDER;
MANAGE_DATA: process(data)
end process MANAGE_DATA;
end architecture behavioral;
\ No newline at end of file
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