Verified Commit 25ceaef6 authored by Javinator9889's avatar Javinator9889 🎼

Updated files

parent a026b1bf
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.math_real.all;
entity ORCHESTRATOR is
end ORCHESTRATOR;
architecture Behavioral of ORCHESTRATOR is
component basic_uart
port (
clk: in std_logic;
reset: in std_logic;
rx_data: out std_logic_vector(7 downto 0);
rx_enable: out std_logic;
tx_data: in std_logic_vector(7 downto 0);
tx_enable: in std_logic;
tx_ready: out std_logic;
rx: in std_logic;
tx: out std_logic
);
end component;
component stepperMotor
port (
clk: in std_logic;
dir: in std_logic;
enable: in std_logic;
clockOut: in std_logic;
dirOut: out std_logic;
enableOut: out std_logic
);
end component;
signal clk : std_logic;
signal reset : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
signal rx_enable : std_logic;
signal tx_data : std_logic_vector(7 downto 0);
signal tx_enable : std_logic;
signal tx_ready : std_logic;
signal rx : std_logic;
signal tx : std_logic;
signal dir : std_logic;
signal enable : std_logic;
signal clockOut : std_logic;
signal dirOut : std_logic;
signal enableOut : std_logic;
begin
end architecture Behavioral;
\ No newline at end of file
......@@ -5,7 +5,8 @@ entity orchestrator is
port (
clk: in std_logic;
clkOut: out std_logic;
uart_rx: in std_logic;
uart_tx: out std_logic
dirOut: out std_logic;
enableOutVector: out std_logic_vector (5 downto 0);
);
......
......@@ -10,20 +10,10 @@ entity stepperMotor is
);
end entity stepperMotor;
architecture behavioral of stepperMotor is
-- Orchestrator
signal tmp : std_logic := '0';
signal count: std_logic_vector (17 downto 0) := (others=>'0');
--signal count_steps: std_logic_vector (5 downto 0) := (others=>'0');
--signal max_steps: std_logic_vector(5 downto 0) := ;
architecture behavioral of stepperMotor is
begin
ENB : process (enable)
begin
if(enable='1') then
......@@ -33,17 +23,4 @@ begin
end if;
end process;
-- Orchestrator
DIVIDER : process(clk, dir)
begin
if(clk'event and clk='1') then
count <= count + 1;
if (count = "11000011010100000") then -- If the clk operates at 100 MHz, its clock cycle is 0.000 000 01 second = 10 ns.
tmp <= NOT tmp;
count <= (others=>'0');
end if;
end if;
clockOut <= tmp;
end process;
end behavioral;
{
"folders": [
{
"path": "."
}
],
"settings": {}
}
\ No newline at end of file
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