Verified Commit 6d035109 authored by Javinator9889's avatar Javinator9889 🎼

Edited UTILITIES for using std_logic

parent b11b3582
library IEEE;
USE IEEE.std_logic_1164.all;
package UTILITIES is
function get_movement_from_binary_code(input_value: bit_vector) return bit_vector;
function get_motor_from_binary_code(input_value: bit_vector) return bit_vector;
function get_movement_from_binary_code(input_value: std_logic_vector) return std_logic_vector;
function get_motor_from_binary_code(input_value: std_logic_vector) return std_logic_vector;
end package UTILITIES;
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.math_real.all;
entity ORCHESTRATOR is
end ORCHESTRATOR;
architecture Behavioral of ORCHESTRATOR is
component basic_uart
port (
clk: in std_logic;
reset: in std_logic;
rx_data: out std_logic_vector(7 downto 0);
rx_enable: out std_logic;
tx_data: in std_logic_vector(7 downto 0);
tx_enable: in std_logic;
tx_ready: out std_logic;
rx: in std_logic;
tx: out std_logic
);
end component;
component stepperMotor
port (
clk: in std_logic;
dir: in std_logic;
enable: in std_logic;
clockOut: in std_logic;
dirOut: out std_logic;
enableOut: out std_logic
);
end component;
signal clk : std_logic;
signal reset : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
signal rx_enable : std_logic;
signal tx_data : std_logic_vector(7 downto 0);
signal tx_enable : std_logic;
signal tx_ready : std_logic;
signal rx : std_logic;
signal tx : std_logic;
signal dir : std_logic;
signal enable : std_logic;
signal clockOut : std_logic;
signal dirOut : std_logic;
signal enableOut : std_logic;
begin
end architecture Behavioral;
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- Para comunicar con los motores, tendriamos que modificar el process de FSM output, y hacer que los datos llegasen a otro componente por definir.
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- Hacer maquina de estados
- Comentar y entender el codigo de la maquina, así como las signal de sample y counter bits
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library IEEE;
USE IEEE.std_logic_1164.all;
package body UTILITIES is
function get_movement_from_binary_code(input_value: bit_vector) return bit_vector is
function get_movement_from_binary_code(input_value: std_logic_vector) return std_logic_vector is
begin
return input_value(1 downto 0);
end get_movement_from_binary_code;
function get_motor_from_binary_code(input_value: bit_vector) return bit_vector is
function get_motor_from_binary_code(input_value: std_logic_vector) return std_logic_vector is
begin
return input_value(4 downto 2);
end get_motor_from_binary_code;
......
-- Eric Bainville
-- Mar 2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.math_real.all;
entity basic_uart is
generic (
DIVISOR: natural -- DIVISOR = 100,000,000 / (16 x BAUD_RATE)
-- 2400 -> 2604
-- 9600 -> 651
-- 115200 -> 54
-- 1562500 -> 4
-- 2083333 -> 3
);
port (
clk: in std_logic; -- clock
reset: in std_logic; -- reset
-- Client interface
rx_data: out std_logic_vector(7 downto 0); -- received byte
rx_enable: out std_logic; -- validates received byte (1 system clock spike)
tx_data: in std_logic_vector(7 downto 0); -- byte to send
tx_enable: in std_logic; -- validates byte to send if tx_ready is '1'
tx_ready: out std_logic; -- if '1', we can send a new byte, otherwise we won't take it
-- Physical interface
rx: in std_logic;
tx: out std_logic
);
end basic_uart;
architecture Behavioral of basic_uart is
constant COUNTER_BITS : natural := integer(ceil(log2(real(DIVISOR))));
type fsm_state_t is (idle, active); -- common to both RX and TX FSM
type rx_state_t is
record
fsm_state: fsm_state_t; -- FSM state
counter: std_logic_vector(3 downto 0); -- tick count
bits: std_logic_vector(7 downto 0); -- received bits
nbits: std_logic_vector(3 downto 0); -- number of received bits (includes start bit)
enable: std_logic; -- signal we received a new byte
end record;
type tx_state_t is
record
fsm_state: fsm_state_t; -- FSM state
counter: std_logic_vector(3 downto 0); -- tick count
bits: std_logic_vector(8 downto 0); -- bits to emit, includes start bit
nbits: std_logic_vector(3 downto 0); -- number of bits left to send
ready: std_logic; -- signal we are accepting a new byte
end record;
signal rx_state,rx_state_next: rx_state_t;
signal tx_state,tx_state_next: tx_state_t;
signal sample: std_logic; -- 1 clk spike at 16x baud rate
signal sample_counter: std_logic_vector(COUNTER_BITS-1 downto 0); -- should fit values in 0..DIVISOR-1
begin
-- sample signal at 16x baud rate, 1 CLK spikes
sample_process: process (clk,reset) is
begin
if reset = '1' then
sample_counter <= (others => '0');
sample <= '0';
elsif rising_edge(clk) then
if sample_counter = DIVISOR-1 then
sample <= '1';
sample_counter <= (others => '0');
else
sample <= '0';
sample_counter <= sample_counter + 1;
end if;
end if;
end process;
-- RX, TX state registers update at each CLK, and RESET
reg_process: process (clk,reset) is
begin
if reset = '1' then
rx_state.fsm_state <= idle;
rx_state.bits <= (others => '0');
rx_state.nbits <= (others => '0');
rx_state.enable <= '0';
tx_state.fsm_state <= idle;
tx_state.bits <= (others => '1');
tx_state.nbits <= (others => '0');
tx_state.ready <= '1';
elsif rising_edge(clk) then
rx_state <= rx_state_next;
tx_state <= tx_state_next;
end if;
end process;
-- RX FSM
rx_process: process (rx_state,sample,rx) is
begin
case rx_state.fsm_state is
when idle =>
rx_state_next.counter <= (others => '0');
rx_state_next.bits <= (others => '0');
rx_state_next.nbits <= (others => '0');
rx_state_next.enable <= '0';
if rx = '0' then
-- start a new byte
rx_state_next.fsm_state <= active;
else
-- keep idle
rx_state_next.fsm_state <= idle;
end if;
when active =>
rx_state_next <= rx_state;
if sample = '1' then
if rx_state.counter = 8 then
-- sample next RX bit (at the middle of the counter cycle)
if rx_state.nbits = 9 then
rx_state_next.fsm_state <= idle; -- back to idle state to wait for next start bit
rx_state_next.enable <= rx; -- OK if stop bit is '1'
else
rx_state_next.bits <= rx & rx_state.bits(7 downto 1);
rx_state_next.nbits <= rx_state.nbits + 1;
end if;
end if;
rx_state_next.counter <= rx_state.counter + 1;
end if;
end case;
end process;
-- RX output
rx_output: process (rx_state) is
begin
rx_enable <= rx_state.enable;
rx_data <= rx_state.bits;
end process;
-- TX FSM
tx_process: process (tx_state,sample,tx_enable,tx_data) is
begin
case tx_state.fsm_state is
when idle =>
if tx_enable = '1' then
-- start a new bit
tx_state_next.bits <= tx_data & '0'; -- data & start
tx_state_next.nbits <= "0000" + 10; -- send 10 bits (includes '1' stop bit)
tx_state_next.counter <= (others => '0');
tx_state_next.fsm_state <= active;
tx_state_next.ready <= '0';
else
-- keep idle
tx_state_next.bits <= (others => '1');
tx_state_next.nbits <= (others => '0');
tx_state_next.counter <= (others => '0');
tx_state_next.fsm_state <= idle;
tx_state_next.ready <= '1';
end if;
when active =>
tx_state_next <= tx_state;
if sample = '1' then
if tx_state.counter = 15 then
-- send next bit
if tx_state.nbits = 0 then
-- turn idle
tx_state_next.bits <= (others => '1');
tx_state_next.nbits <= (others => '0');
tx_state_next.counter <= (others => '0');
tx_state_next.fsm_state <= idle;
tx_state_next.ready <= '1';
else
tx_state_next.bits <= '1' & tx_state.bits(8 downto 1);
tx_state_next.nbits <= tx_state.nbits - 1;
end if;
end if;
tx_state_next.counter <= tx_state.counter + 1;
end if;
end case;
end process;
-- TX output
tx_output: process (tx_state) is
begin
tx_ready <= tx_state.ready;
tx <= tx_state.bits(0);
end process;
end Behavioral;
# leds
set_property PACKAGE_PIN U16 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property PACKAGE_PIN U19 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property PACKAGE_PIN V19 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property PACKAGE_PIN W18 [get_ports {led[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property PACKAGE_PIN U15 [get_ports {led[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
set_property PACKAGE_PIN U14 [get_ports {led[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
set_property PACKAGE_PIN V14 [get_ports {led[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
#SYS_CLOCK
set_property PACKAGE_PIN W5 [get_ports sys_clk]
set_property IOSTANDARD LVCMOS33 [get_ports sys_clk]
create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports sys_clk]
#UART
set_property PACKAGE_PIN B18 [get_ports uart_rx]
set_property IOSTANDARD LVCMOS33 [get_ports uart_rx]
set_property PACKAGE_PIN A18 [get_ports uart_tx]
set_property IOSTANDARD LVCMOS33 [get_ports uart_tx]
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NET led(0) LOC = "U16" | IOSTANDARD=LVCMOS33;
NET led(1) LOC = "E19" | IOSTANDARD=LVCMOS33;
NET led(2) LOC = "U19" | IOSTANDARD=LVCMOS33;
NET led(3) LOC = "V19" | IOSTANDARD=LVCMOS33;
NET led(4) LOC = "W18" | IOSTANDARD=LVCMOS33;
NET led(5) LOC = "U15" | IOSTANDARD=LVCMOS33;
NET led(6) LOC = "U14" | IOSTANDARD=LVCMOS33;
NET led(7) LOC = "V14" | IOSTANDARD=LVCMOS33;
NET sys_clk TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
NET sys_clk LOC = "W5" | IOSTANDARD=LVCMOS33;
net uart_rx LOC=A18 | IOSTANDARD=LVCMOS33;
net uart_tx LOC=B18 | IOSTANDARD=LVCMOS33;
-- EB Mar 2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity t_serial is
port(
sys_clk: in std_logic; -- 100 MHz system clock
led: out std_logic_vector(7 downto 0);
uart_rx: in std_logic;
uart_tx: out std_logic
);
end t_serial;
architecture Behavioral of t_serial is
component basic_uart is
generic (
DIVISOR: natural
);
port (
clk: in std_logic; -- system clock
reset: in std_logic;
-- Client interface
rx_data: out std_logic_vector(7 downto 0); -- received byte
rx_enable: out std_logic; -- validates received byte (1 system clock spike)
tx_data: in std_logic_vector(7 downto 0); -- byte to send
tx_enable: in std_logic; -- validates byte to send if tx_ready is '1'
tx_ready: out std_logic; -- if '1', we can send a new byte, otherwise we won't take it
-- Physical interface
rx: in std_logic;
tx: out std_logic
);
end component;
type fsm_state_t is (idle, received, emitting);
type state_t is
record
fsm_state: fsm_state_t; -- FSM state
tx_data: std_logic_vector(7 downto 0);
tx_enable: std_logic;
end record;
signal reset: std_logic;
signal uart_rx_data: std_logic_vector(7 downto 0);
signal uart_rx_enable: std_logic;
signal uart_tx_data: std_logic_vector(7 downto 0);
signal uart_tx_enable: std_logic;
signal uart_tx_ready: std_logic;
signal state,state_next: state_t;
begin
basic_uart_inst: basic_uart
generic map (DIVISOR => 2604) -- 2400
port map (
clk => sys_clk, reset => reset,
rx_data => uart_rx_data, rx_enable => uart_rx_enable,
tx_data => uart_tx_data, tx_enable => uart_tx_enable, tx_ready => uart_tx_ready,
rx => uart_rx,
tx => uart_tx
);
fsm_clk: process (sys_clk,reset) is
begin
if reset = '1' then
state.fsm_state <= idle;
state.tx_data <= (others => '0');
state.tx_enable <= '0';
else
if rising_edge(sys_clk) then
state <= state_next;
end if;
end if;
end process;
fsm_next: process (state,uart_rx_enable,uart_rx_data,uart_tx_ready) is
begin
state_next <= state;
case state.fsm_state is
when idle =>
if uart_rx_enable = '1' then
state_next.tx_data <= uart_rx_data;
state_next.tx_enable <= '0';
state_next.fsm_state <= received;
end if;
when received =>
if uart_tx_ready = '1' then
state_next.tx_enable <= '1';
state_next.fsm_state <= emitting;
end if;
when emitting =>
if uart_tx_ready = '0' then
state_next.tx_enable <= '0';
state_next.fsm_state <= idle;
end if;
end case;
end process;
fsm_output: process (state) is
begin
uart_tx_enable <= state.tx_enable;
uart_tx_data <= state.tx_data;
led <= state.tx_data;
end process;
end Behavioral;
import serial
ser = serial.Serial("COM11",baudrate=2400)
ser.write(b'b')
ser.close()
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