Verified Commit a026b1bf authored by Javinator9889's avatar Javinator9889 🎼

Created output pins that will have the FPGA - revision needed

parent 0fa4b45e
library work;
use work.UTILITIES.all;
entity bitStringController is
port (
bitString: in std_logic_vector (7 downto 0);
motor: out std_logic_vector (5 downto 0);
movement: out std_logic;
pulses: out integer
);
end bitStringController;
architecture behavioral of bitStringController is
begin
signal codeMotor: std_logic_vector (2 downto 0)
signal codeMove: std_logic_vector (1 downto 0)
signal enableVector: std_logic_vector ( 5 downto 0);
signal codeMoveToPulses: integer;
signal direction: std_logic;
bitController: process(bitString)
begin
codeMotor <= get_motor_from_binary_code(bitString);
codeMove <= get_movement_from_binary_code(bitString);
case codeMotor is
when "000" => enableVector <= "000001";
when "001" => enableVector <= "000010";
when "010" => enableVector <= "000100";
when "011" => enableVector <= "001000";
when "100" => enableVector <= "010000";
when "101" => enableVector <= "100000";
when others => enableVector <= "000000";
end case;
case codeMove is
when "00" => direction <= '0'; codeMoveToPulses <= '50';
when "01" => direction <= '1'; codeMoveToPulses <= '50';
when "10" => direction <= '0'; codeMoveToPulses <= '100';
when "11" => direction <= '1'; codeMoveToPulses <= '100';
end case;
motor <= enableVector;
movement <= direction;
pulses <= codeMoveToPulses;
end process;
end behavioral;
\ No newline at end of file
......@@ -11,7 +11,7 @@ entity motorOrchestrator is
dirOut: out std_logic;
enableOutVector: out std_logic_vector (5 downto 0);
clkOut: out std_logic
) ;
);
end motorOrchestrator;
architecture behavioral of motorOrchestrator is
......@@ -57,11 +57,7 @@ begin
DIRECTION : process (dirIn)
begin
if(dirIn='1') then
dirOut <= '1';
else
dirOut <= '0';
end if;
dirOut <= dirIn;
end process;
end behavioral ; -- behavioral
......@@ -5,7 +5,9 @@ entity orchestrator is
port (
clk: in std_logic;
clkOut: out std_logic
clkOut: out std_logic;
dirOut: out std_logic;
enableOutVector: out std_logic_vector (5 downto 0);
);
end orchestrator;
......@@ -25,7 +27,7 @@ architecture behavioral of orchestrator is
port (
bitString: in std_logic_vector (7 downto 0);
motor: out std_logic_vector (2 downto 0);
motor: out std_logic_vector (5 downto 0);
movement: out std_logic;
pulses: out integer;
)
......@@ -56,16 +58,21 @@ architecture behavioral of orchestrator is
-- Signals for parsing the input data
signal bit_string: std_logic_vector (7 downto 0);
signal motor_number: std_logic_vector (2 downto 0);
signal motor_number: std_logic_vector (5 downto 0);
signal movement: std_logic;
signal pulses: integer;
-- Signals for managing the motors
begin
serial: t_serial port map (sys_clk, data, uart_rx, uart_tx);
bit_controller: bitStringController port map (bit_string, motor_number, movement, pulses);
motor_handler: motorOrchestrator port map (clk => clkOut,
nPulses => pulses,
enableIn => motor_number,
dirIn => movement,
dirOut => dirOut,
enableOutVector => enableOutVector,
clkOut => clkOut);
CLK_DIVIDER: process(clk)
begin
......@@ -82,7 +89,7 @@ begin
MANAGE_DATA: process(data)
begin
bit_string <= data;
end process MANAGE_DATA;
end architecture behavioral;
\ No newline at end of file
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