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Commits (22)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.math_real.all;
entity basic_uart is
generic (
DIVISOR: natural -- DIVISOR = 100,000,000 / (16 x BAUD_RATE)
-- 2400 -> 2604
-- 9600 -> 651
-- 115200 -> 54
-- 1562500 -> 4
-- 2083333 -> 3
);
port (
clk: in std_logic; -- clock
reset: in std_logic; -- reset
-- Client interface
rx_data: out std_logic_vector(7 downto 0); -- received byte
rx_enable: out std_logic; -- validates received byte (1 system clock spike)
tx_data: in std_logic_vector(7 downto 0); -- byte to send
tx_enable: in std_logic; -- validates byte to send if tx_ready is '1'
tx_ready: out std_logic; -- if '1', we can send a new byte, otherwise we won't take it
-- Physical interface
rx: in std_logic;
tx: out std_logic
);
end basic_uart;
architecture Behavioral of basic_uart is
constant COUNTER_BITS : natural := integer(ceil(log2(real(DIVISOR))));
type fsm_state_t is (idle, active); -- common to both RX and TX FSM
type rx_state_t is
record
fsm_state: fsm_state_t; -- FSM state
counter: std_logic_vector(3 downto 0); -- tick count
bits: std_logic_vector(7 downto 0); -- received bits
nbits: std_logic_vector(3 downto 0); -- number of received bits (includes start bit)
enable: std_logic; -- signal we received a new byte
end record;
type tx_state_t is
record
fsm_state: fsm_state_t; -- FSM state
counter: std_logic_vector(3 downto 0); -- tick count
bits: std_logic_vector(8 downto 0); -- bits to emit, includes start bit
nbits: std_logic_vector(3 downto 0); -- number of bits left to send
ready: std_logic; -- signal we are accepting a new byte
end record;
signal rx_state,rx_state_next: rx_state_t;
signal tx_state,tx_state_next: tx_state_t;
signal sample: std_logic; -- 1 clk spike at 16x baud rate
signal sample_counter: std_logic_vector(COUNTER_BITS-1 downto 0); -- should fit values in 0..DIVISOR-1
begin
-- sample signal at 16x baud rate, 1 CLK spikes
sample_process: process (clk,reset) is
begin
if reset = '1' then
sample_counter <= (others => '0');
sample <= '0';
elsif rising_edge(clk) then
if sample_counter = DIVISOR-1 then
sample <= '1';
sample_counter <= (others => '0');
else
sample <= '0';
sample_counter <= sample_counter + 1;
end if;
end if;
end process;
-- RX, TX state registers update at each CLK, and RESET
reg_process: process (clk,reset) is
begin
if reset = '1' then
rx_state.fsm_state <= idle;
rx_state.bits <= (others => '0');
rx_state.nbits <= (others => '0');
rx_state.enable <= '0';
tx_state.fsm_state <= idle;
tx_state.bits <= (others => '1');
tx_state.nbits <= (others => '0');
tx_state.ready <= '1';
elsif rising_edge(clk) then
rx_state <= rx_state_next;
tx_state <= tx_state_next;
end if;
end process;
-- RX FSM
rx_process: process (rx_state,sample,rx) is
begin
case rx_state.fsm_state is
when idle =>
rx_state_next.counter <= (others => '0');
rx_state_next.bits <= (others => '0');
rx_state_next.nbits <= (others => '0');
rx_state_next.enable <= '0';
if rx = '0' then
-- start a new byte
rx_state_next.fsm_state <= active;
else
-- keep idle
rx_state_next.fsm_state <= idle;
end if;
when active =>
rx_state_next <= rx_state;
if sample = '1' then
if rx_state.counter = 8 then
-- sample next RX bit (at the middle of the counter cycle)
if rx_state.nbits = 9 then
rx_state_next.fsm_state <= idle; -- back to idle state to wait for next start bit
rx_state_next.enable <= rx; -- OK if stop bit is '1'
else
rx_state_next.bits <= rx & rx_state.bits(7 downto 1);
rx_state_next.nbits <= rx_state.nbits + 1;
end if;
end if;
rx_state_next.counter <= rx_state.counter + 1;
end if;
end case;
end process;
-- RX output
rx_output: process (rx_state) is
begin
rx_enable <= rx_state.enable;
rx_data <= rx_state.bits;
end process;
-- TX FSM
tx_process: process (tx_state,sample,tx_enable,tx_data) is
begin
case tx_state.fsm_state is
when idle =>
if tx_enable = '1' then
-- start a new bit
tx_state_next.bits <= tx_data & '0'; -- data & start
tx_state_next.nbits <= "0000" + 10; -- send 10 bits (includes '1' stop bit)
tx_state_next.counter <= (others => '0');
tx_state_next.fsm_state <= active;
tx_state_next.ready <= '0';
else
-- keep idle
tx_state_next.bits <= (others => '1');
tx_state_next.nbits <= (others => '0');
tx_state_next.counter <= (others => '0');
tx_state_next.fsm_state <= idle;
tx_state_next.ready <= '1';
end if;
when active =>
tx_state_next <= tx_state;
if sample = '1' then
if tx_state.counter = 15 then
-- send next bit
if tx_state.nbits = 0 then
-- turn idle
tx_state_next.bits <= (others => '1');
tx_state_next.nbits <= (others => '0');
tx_state_next.counter <= (others => '0');
tx_state_next.fsm_state <= idle;
tx_state_next.ready <= '1';
else
tx_state_next.bits <= '1' & tx_state.bits(8 downto 1);
tx_state_next.nbits <= tx_state.nbits - 1;
end if;
end if;
tx_state_next.counter <= tx_state.counter + 1;
end if;
end case;
end process;
-- TX output
tx_output: process (tx_state) is
begin
tx_ready <= tx_state.ready;
tx <= tx_state.bits(0);
end process;
end Behavioral;
library work;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bitStringController is
port (
bitString: in std_logic_vector (7 downto 0); -- Received data
motor: out std_logic_vector (5 downto 0); -- Selected motor
movement: out std_logic; -- Direcction
pulses: out std_logic_vector (6 downto 0) -- Degrees
);
end bitStringController;
architecture behavioral of bitStringController is
-- Signals related with the relevant bits
signal codeMotor: std_logic_vector (2 downto 0);
signal codeMove: std_logic_vector (1 downto 0);
begin
-- Covered in documentation
bitStringControl : process(bitString)
begin
codeMotor(0) <= bitString(0);
codeMotor(1) <= bitString(1);
codeMotor(2) <= bitString(2);
codeMove(0) <= bitString(3);
codeMove(1) <= bitString(4);
end process;
-- Covered in documentation
cMotorProcess: process(codeMotor)
begin
case codeMotor is
when "000" => motor <= "000001";
when "001" => motor <= "000010";
when "010" => motor <= "000100";
when "011" => motor <= "001000";
when "100" => motor <= "010000";
when "101" => motor <= "100000";
when others => motor <= "000000";
end case;
end process;
-- Covered in documentation
cMoveProcess: process(codeMove)
begin
case codeMove is
when "00" => movement <= '0'; pulses <= "0110010";
when "01" => movement <= '1'; pulses <= "0110010";
when "10" => movement <= '0'; pulses <= "1100100";
when "11" => movement <= '1'; pulses <= "1100100";
when others => movement <= '0'; pulses <= "0000000";
end case;
end process;
-- Covered in documentation
cPulsesProcess: process(codeMove)
begin
case codeMove is
when "00" => pulses <= "0110010";
when "01" => pulses <= "0110010";
when "10" => pulses <= "1100100";
when "11" => pulses <= "1100100";
when others => pulses <= "0000000";
end case;
end process;
end behavioral;
\ No newline at end of file
#JA PINS
set_property PACKAGE_PIN J1 [get_ports {clkOut}] #Motor clock
set_property IOSTANDARD LVCMOS33 [get_ports {clkOut}]
set_property PACKAGE_PIN L2 [get_ports {dirOut}] #Direction
set_property IOSTANDARD LVCMOS33 [get_ports {dirOut}]
set_property PACKAGE_PIN J2 [get_ports {enableMotor[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {enableMotor[0]}]
set_property PACKAGE_PIN G2 [get_ports {enableMotor[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {enableMotor[1]}]
set_property PACKAGE_PIN H1 [get_ports {enableMotor[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {enableMotor[2]}]
set_property PACKAGE_PIN K2 [get_ports {enableMotor[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {enableMotor[3]}]
set_property PACKAGE_PIN H2 [get_ports {enableMotor[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {enableMotor[4]}]
set_property PACKAGE_PIN G3 [get_ports {enableMotor[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {enableMotor[5]}]
# ledOutVectors
set_property PACKAGE_PIN U16 [get_ports {ledOutVector[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ledOutVector[0]}]
set_property PACKAGE_PIN E19 [get_ports {ledOutVector[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ledOutVector[1]}]
set_property PACKAGE_PIN U19 [get_ports {ledOutVector[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ledOutVector[2]}]
set_property PACKAGE_PIN V19 [get_ports {ledOutVector[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ledOutVector[3]}]
set_property PACKAGE_PIN W18 [get_ports {ledOutVector[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ledOutVector[4]}]
set_property PACKAGE_PIN U15 [get_ports {ledOutVector[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ledOutVector[5]}]
set_property PACKAGE_PIN U14 [get_ports {ledOutVector[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ledOutVector[6]}]
set_property PACKAGE_PIN V14 [get_ports {ledOutVector[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ledOutVector[7]}]
#SYS_CLOCK
set_property PACKAGE_PIN W5 [get_ports clk] #100 MHz Oscillator on port W5
set_property IOSTANDARD LVCMOS33 [get_ports clk]
#UART PINS
set_property PACKAGE_PIN B18 [get_ports uart_rx_pin]
set_property IOSTANDARD LVCMOS33 [get_ports uart_rx_pin]
set_property PACKAGE_PIN A18 [get_ports uart_tx_pin]
set_property IOSTANDARD LVCMOS33 [get_ports uart_tx_pin]
\ No newline at end of file
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity t_serial is
port(
sys_clk: in std_logic; -- 100 MHz system clock
led: out std_logic_vector(7 downto 0);
uart_rx: in std_logic;
uart_tx: out std_logic
);
end t_serial;
architecture Behavioral of t_serial is
component basic_uart is
generic (
DIVISOR: natural
);
port (
clk: in std_logic; -- system clock
reset: in std_logic;
-- Client interface
rx_data: out std_logic_vector(7 downto 0); -- received byte
rx_enable: out std_logic; -- validates received byte (1 system clock spike)
tx_data: in std_logic_vector(7 downto 0); -- byte to send
tx_enable: in std_logic; -- validates byte to send if tx_ready is '1'
tx_ready: out std_logic; -- if '1', we can send a new byte, otherwise we won't take it
-- Physical interface
rx: in std_logic;
tx: out std_logic
);
end component;
type fsm_state_t is (idle, received, emitting);
type state_t is
record
fsm_state: fsm_state_t; -- FSM state
tx_data: std_logic_vector(7 downto 0);
tx_enable: std_logic;
end record;
signal reset: std_logic;
signal uart_rx_data: std_logic_vector(7 downto 0);
signal uart_rx_enable: std_logic;
signal uart_tx_data: std_logic_vector(7 downto 0);
signal uart_tx_enable: std_logic;
signal uart_tx_ready: std_logic;
signal state,state_next: state_t;
begin
basic_uart_inst: basic_uart
generic map (DIVISOR => 2604) -- 2400
port map (
clk => sys_clk, reset => reset,
rx_data => uart_rx_data, rx_enable => uart_rx_enable,
tx_data => uart_tx_data, tx_enable => uart_tx_enable, tx_ready => uart_tx_ready,
rx => uart_rx,
tx => uart_tx
);
fsm_clk: process (sys_clk,reset) is
begin
if reset = '1' then
state.fsm_state <= idle;
state.tx_data <= (others => '0');
state.tx_enable <= '0';
else
if rising_edge(sys_clk) then
state <= state_next;
end if;
end if;
end process;
fsm_next: process (state,uart_rx_enable,uart_rx_data,uart_tx_ready) is
begin
state_next <= state;
case state.fsm_state is
when idle =>
if uart_rx_enable = '1' then
state_next.tx_data <= uart_rx_data;
state_next.tx_enable <= '0';
state_next.fsm_state <= received;
end if;
when received =>
if uart_tx_ready = '1' then
state_next.tx_enable <= '1';
state_next.fsm_state <= emitting;
end if;
when emitting =>
if uart_tx_ready = '0' then
state_next.tx_enable <= '0';
state_next.fsm_state <= idle;
end if;
end case;
end process;
fsm_output: process (state) is
begin
uart_tx_enable <= state.tx_enable;
uart_tx_data <= state.tx_data;
led <= state.tx_data;
end process;
end Behavioral;
\ No newline at end of file
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity motorOrchestrator is
generic(
init_val: std_logic := '0'
);
port (
clk: in std_logic; -- Divided clock
nPulses: in std_logic_vector (6 downto 0); -- Degrees (bit)
enableIn: in std_logic_vector (5 downto 0); -- Selected motor (bit)
dirIn: in std_logic; -- Direction (bit)
pulsesFinishedIn: in std_logic := init_val; -- Aux signal FSM
pulsesFinishedOut: out std_logic := init_val; -- Aux signal FSM
dirOut: out std_logic; -- Output signal (direction)
enableOut: out std_logic_vector (5 downto 0) -- Output signal (selected motor)
);
end motorOrchestrator;
architecture behavioral of motorOrchestrator is
-- Signal to control pulses of the motor
signal counter : std_logic_vector (6 downto 0) := (others => '0');
-- Inversed logic in enable module A4988
component stepperMotor is
port (
enable: in std_logic;
enableOut: out std_logic
);
end component;
begin
-- Motor components needed
m0: stepperMotor port map ( enable => enableIn(0),
enableOut => enableOut(0));
m1: stepperMotor port map ( enable => enableIn(1),
enableOut => enableOut(1));
m2: stepperMotor port map ( enable => enableIn(2),
enableOut => enableOut(2));
m3: stepperMotor port map ( enable => enableIn(3),
enableOut => enableOut(3));
m4: stepperMotor port map ( enable => enableIn(4),
enableOut => enableOut(4));
m5: stepperMotor port map ( enable => enableIn(5),
enableOut => enableOut(5));
-- Process to check how many pulses have been done
nSTEP : process (clk)
begin
if clk'event and clk='1' then
if counter <= nPulses and pulsesFinishedIn='0' then
counter <= counter + 1;
pulsesFinishedOut <= '0';
else
counter <= (others => '0');
pulsesFinishedOut <= '1';
end if;
end if;
end process;
-- Process to assist the direction output
DIRECTION : process (dirIn)
begin
dirOut <= dirIn;
end process;
end behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity orchestrator is
port (
clk: in std_logic; -- Oscillator Pin
uart_rx_pin: in std_logic; -- RX Pin
uart_tx_pin: out std_logic; -- TX Pin
clkOut: out std_logic; -- Motor Clock output
dirOut: out std_logic; -- Motor direction output
enableMotor: out std_logic_vector(5 downto 0); -- Motor enabled vector
ledOutVector: out std_logic_vector (7 downto 0) -- LEDs Pin
);
end orchestrator;
architecture behavioral of orchestrator is
-- Signals for dividing the clock
signal dividedClkEvent: std_logic := '0';
signal counter: std_logic_vector (17 downto 0) := (others => '0');
-- Signals for receiving input data from USB
signal sys_clk: std_logic;
signal data: std_logic_vector (7 downto 0);
signal dataMotor: std_logic_vector (7 downto 0);
-- Signals for parsing the input data
signal motor_number: std_logic_vector (5 downto 0);
signal movement: std_logic;
signal pulses: std_logic_vector (6 downto 0);
-- Signal for active wait on motors
signal pulsesFinishedIn: std_logic := '0';
signal pulsesFinishedOut: std_logic := '0';
-- Signal for changed data
signal hasChanged: std_logic;
-- FSM to accomplish the casuistic covered in the documentation
type stateType is (A, B);
signal state_reg: stateType := B;
signal state_next: stateType;
component t_serial is
port (
sys_clk: in std_logic; -- Oscillator
uart_rx: in std_logic; -- RX PIN
led: out std_logic_vector (7 downto 0); -- Data
uart_tx: out std_logic
);
end component;
component bitStringController is
port (
bitString: in std_logic_vector (7 downto 0); -- Data
motor: out std_logic_vector (5 downto 0); -- Motor enabled vector
movement: out std_logic; -- Motor Direction
pulses: out std_logic_vector (6 downto 0) -- Motor degrees
);
end component;
component motorOrchestrator is
port (
clk: in std_logic; -- Motor clock
nPulses: in std_logic_vector (6 downto 0); -- Motor degrees (input data)
enableIn: in std_logic_vector (5 downto 0); -- Motor enabled vector (input data)
dirIn: in std_logic; -- Motor direction (input data)
pulsesFinishedIn: in std_logic; -- AUX Signal
pulsesFinishedOut: out std_logic; -- AUX Signal
dirOut: out std_logic; -- Direction out
enableOut: out std_logic_vector (5 downto 0) -- Motor enabled vector (out data)
);
end component;
begin
serial: t_serial port map (sys_clk => clk,
led => data,
uart_rx => uart_rx_pin,
uart_tx => uart_tx_pin);
bit_controller: bitStringController port map (bitString => dataMotor,
motor => motor_number,
movement => movement,
pulses => pulses);
motor_handler: motorOrchestrator port map (clk => dividedClkEvent,
nPulses => pulses,
enableIn => motor_number,
dirIn => movement,
pulsesFinishedIn => pulsesFinishedIn,
pulsesFinishedOut => pulsesFinishedOut,
dirOut => dirOut,
enableOut => enableMotor);
-- Process to create the divided clock from the oscillator
CLK_DIVIDER: process(clk)
begin
if (clk'event and clk = '1') then
counter <= counter + 1;
if (counter = "11000011010100000") then
dividedClkEvent <= not dividedClkEvent;
counter <= (others => '0');
end if;
end if;
clkOut <= dividedClkEvent;
end process CLK_DIVIDER;
-- Received new data
AUX_EVENT: process(dividedClkEvent)
variable newdata: std_logic_vector(7 downto 0) := "11110000";
begin
if (data /= newdata) then
hasChanged <= '1';
newdata := data;
else
hasChanged <= '0';
end if;
end process;
-- FSM RESET to default
FSM_RESET_ASYNC: process(dividedClkEvent, hasChanged)
begin
if hasChanged = '1' then
state_reg <= A;
elsif falling_edge(dividedClkEvent) then
state_reg <= state_next;
end if;
end process;
-- FSM transitions
FSM_ACT: process(pulsesFinishedOut, hasChanged, state_reg)
begin
ledOutVector <= data;
state_next <= state_reg;
pulsesFinishedIn <= '0';
dataMotor <= data;
case state_reg is
when A =>
if pulsesFinishedOut = '0' then
pulsesFinishedIn <= '0';
dataMotor <= data;
state_next <= B;
end if;
when B =>
if pulsesFinishedOut = '1' then
pulsesFinishedIn <= '1';
dataMotor <= "11111111";
state_next <= B;
end if;
end case;
end process;
end architecture behavioral;
\ No newline at end of file
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity stepperMotor is
port (
enable: in std_logic; -- Enable data
enableOut: out std_logic -- Enable out signal
);
end entity stepperMotor;
architecture behavioral of stepperMotor is
begin
-- Process to reverse the logic for the A4988 module
ENB : process (enable)
begin
if(enable='1') then
enableOut <= '0';
else
enableOut <= '1';
end if;
end process;
end behavioral;