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The relaxed SIMD proposal is now in Phase 4. We should consider to implement it.
Ref: https://github.com/WebAssembly/relaxed-simd
Implement the whole spec of the relaxed SIMD proposal, including the interpreter, AOT, and JIT.
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Comment:
according to the binary format of instruction OpCodes, relaxed-simd instructions need 3-byte length of OpCode: 0xFD, 0x01, 0x00 to 0x2F.
0xFD
0x01
0x00
0x2F
As the current WasmEdge structure, we only supports 2-byte OpCode. Refactoring before implement this proposal is necessary.
Comment: according to the binary format of instruction OpCodes, relaxed-simd instructions need 3-byte length of OpCode: 0xFD, 0x01, 0x00 to 0x2F. As the current WasmEdge structure, we only supports 2-byte OpCode. Refactoring before implement this proposal is necessary.
Comment: This fixed in #3320 .
LFsWang
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Summary
The relaxed SIMD proposal is now in Phase 4. We should consider to implement it.
Ref: https://github.com/WebAssembly/relaxed-simd
Details
Implement the whole spec of the relaxed SIMD proposal, including the interpreter, AOT, and JIT.
Appendix
No response
The text was updated successfully, but these errors were encountered: