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CLFLUSH causes TLB assertion error #862
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A possible fix is to change line 257 to:
Line 257 in c890e6b
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Thanks for the fix @Lukas-Zenick. I wonder if this error only occurs for the timing CPU or if it also happens when using the O3 CPU? If it's only the timing CPU, then maybe we should update the |
ivanaamit
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that referenced
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Jun 3, 2024
Fixed the assertion statement in the cpu's translation.hh file so that it doesn't fail the assertion if the cache is clean. I compile this c code to `test` ```c #include <stdio.h> static inline void clflush(volatile void *p) { __asm__ volatile ("clflush (%0)" : : "r"(p) : "memory"); } int main() { int data = 42; // Example variable printf("Value before clflush: %d\n", data); clflush(&data); printf("Value after clflush: %d\n", data); return 0; } ``` And run it with this script `./build/X86/gem5.opt configs/learning_gem5/part1/two_level.py ./test` In order to verify that it no longer fails the assertion check. GitHub Issue: #862 Change-Id: I6004662e7c99f637ba0ddb07d205d1657708e99f
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Describe the bug
Executing
clflush
instruction in FS mode caused this assertion error,The problem seems to be that,
clflush*
is a store instruction.BaseMMU::Write
mode.BaseMMU::Read
as the mem request caused byclflush
is aisCacheClean
request. https://github.com/gem5/gem5/blob/v23.1.0.0/src/arch/x86/tlb.cc#L556-L564Affects version
v23.1
gem5 Modifications
N/A
Additional information
Related issue: #226
Related change: #592
Reverting #592 fixes the error on my side, but it's not ideal due to issue #226.
I think we can make the
clflush*
instructions to be load instructions, but I'm not sure if that change is functionally correct.The text was updated successfully, but these errors were encountered: