MIPS single-cycle processor

Simple Computer Architecture using direct mapped cache memory. Designed in VHDL and Quartus.

Tournament Branch Predictor (Hybrid Predictor)

This is a project repository for Maham and Shiza Computer Architecture

Grad school, Adv Computer Architecture, Instruction Pipeline project. Pipelining is a technique where multiple instructions are overlapped during execution. Pipeline is divided into stages and these stages are connected with one another to form a pipe like structure. Instructions enter from one end and exit from another end. Pipelining increases…

7 Stage APEX Pipeline based on instructions flow in a Computer Architecture

Upgrading ARM9TDMI 32-bit processor original version.

Code from labs for COIS 2300 Computer Organization

This project implements a MIPS processor simulator in C++. It interprets a limited set of MIPS assembly, enabling the implementation of a functional processor. The system features an automated assembly-machine code translator and offers modes for testing and execution. Specialized modules handle operations like arithmetic, multiplexing, etc.

MIPS Architecture 32 bit CPU in Verilog Quartus

🏜 Implementation of single-level cache simulator and analyze the performance of various cache architectures using real-world program traces.

Website for the long-term mentoring program in computer architecture.

Some samples of my CS work from the 2019-2020 school year

Herramienta que permite la visualización de los resultados obtenidos de la exploración del diseño de microarquitecturas y procesadores. 🧭📊

Thesaurus: Efficient Cache Compression via Dynamic Clustering -- ASPLOS 2020

2DCC: Cache Compression in Two Dimensions -- DATE 2020

Implementation of MIPS-32 microprocessor

Assignments repository for Computer Organisation Laboratory course, Autumn 2022

in this repos i'm recording some notes , tricks ,code samples which i consider usefull for me and maybe it can help someone who found it.