FlappyBird on VGA Display using Verilog
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Updated
Dec 15, 2016 - Verilog
FlappyBird on VGA Display using Verilog
Computer Design Experiments
This is my final project for digital logic in the third semester of university.
This was the project assignment for the Digital Logic Design course.
Digital Piano: FPGA project in Verilog based on Xilinx Atrix-7 EGO1 - SUSTech's project of course CS207: Digital Logic in Fall 2023 - Score: 120/100
Universal Asynchronous Receiver-Transmitter. Semester project of Digital Logic and System Design course of fall 2017, IIT Delhi.
[sp19] Digital logic, circuit components. Data representation, computer architecture and implementation, assembly language programming.
北京邮电大学“数字逻辑与数字系统”实验课程的电路接线图。
implementation of a machine executes simple operations in general built-in registers in Verilog
A Novel Numeric Decoder Logic Design
Lubin Pappalardo's official Digital Logic Simulator.
同济大学CS《数字逻辑》大作业: 车床仿真系统TongJi University CS digital logic assignment: lathe simulation system
Projects from a second-year computer engineering course on digital logic (written in Verilog)
Digital Logic course's final test (Polytechnic of Milan, 2022/23 A.Y.)
here the notes provided by the seniors who already cracked IITs as well as how much I'll cover for my exams I'll provide my notes as well. If you want you can access the course by these links also
A multilayer perceptron that uses an OOP approach towards solving all 16 digital logic functions.
A nand2tetris-like Project written entirely in ANSI C
Codes written by me in my Digital Logic Design course.
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