SEA-M - Syntax-Encoding Assembler For MOOn-IV is a simple assembler for the MOOn-IV architecture. It is written in Python 3 and is a command-line tool.
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Updated
Jun 6, 2024 - Python
SEA-M - Syntax-Encoding Assembler For MOOn-IV is a simple assembler for the MOOn-IV architecture. It is written in Python 3 and is a command-line tool.
Intel® Performance Counter Monitor (Intel® PCM)
A graphical processor simulator and assembly editor for the RISC-V ISA
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Explored x86 assembly programming using NASM, dived into low-level coding and discovered the inner workings of computer hardware and software.
This project involves the implementation and simulation of a MIPS 5-stage pipelined processor using Verilog. The implementation is based on the MIPS architecture as outlined in the "Computer Organization and Design: The Hardware/Software Interface" and "Digital Design and Computer Architecture"
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8-bit Processor emulator designed and impemented using Java SE
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Sequential & Pipelined implementation of Y86-64 ISA in Verilog
CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] <Semester IV>
ARM processor pipeline implementation. Featuring hazard unit, forwarding unit, SRAM & cache memory.
A custom 16-bit processor with a custom assembly language and emulator, based off of the ARM 32-bit processor.
WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]
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