Veryl: A Modern Hardware Description Language
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Updated
Jun 11, 2024 - Rust
Veryl: A Modern Hardware Description Language
Verilator open-source SystemVerilog simulator and lint system
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
BDD Gherkin implementation in native SystemVerilog, based on UVM.
Free, open-source, and cross-platform analysis tool for Scrabble, Super Scrabble & Literaki. Quickly find top scoring words using given letters and board state. Available in English, French, German, Persian, Polish, Romanian & Spanish.
23년 안에 배포, 24년엔 리팩토링
This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.
A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.
PostCSS plugin to automatically build Cascading Style Sheets (CSS) with Left-To-Right (LTR) and Right-To-Left (RTL) rules using RTLCSS
Quark is a single cycle RV32I RISC-V core, The RTL is written in BlueSpec System Verilog (BSV)
🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Code generation tool for control and status registers
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