system-on-chip
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🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
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Jun 11, 2024 - C
System on Chip toolkit for Amaranth HDL
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Jun 10, 2024 - Python
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
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Jun 12, 2024 - C
The goal of ECE 385 course is to teach students to design, build, and test/debug a digital system, which can be a 16-bit microprocessor, a dedicated logic core, or a system-on-a-chip (SoC) platform
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May 28, 2024 - Verilog
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
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May 28, 2024 - Python
🌌 A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in SystemVerilog. Stage 1, the purpose is to learn how to design a risc-v processor with basic peripherals and the RISC-V instruction set architecture.
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May 17, 2024 - SystemVerilog
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
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May 16, 2024 - SystemVerilog
Embedded Systems Geeks Guadalajara - Collaboration Space
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May 2, 2024 - C
QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.
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Apr 30, 2024 - Assembly
Hardware Abstraction Layer for Atmosic SoCs in the Zephyr Environment
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Apr 18, 2024 - C
Chisel implementation of Neural Processing Unit for System on the Chip
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Apr 6, 2024 - Scala
Examples of using Litex on an Alchitry Cu board
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Feb 4, 2024 - Python
Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedded programs targeted at the microprocessor to control the peripherals
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Nov 24, 2023 - HTML
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