uvm
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Functional verification project for the CORE-V family of RISC-V cores.
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Jun 12, 2024 - Assembly
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
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May 15, 2024 - C++
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
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Jul 28, 2023 - Verilog
Awesome ASIC design verification
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Feb 9, 2022
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
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Nov 25, 2019 - SystemVerilog
Code generation tool for control and status registers
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Jun 11, 2024 - Ruby
Network on Chip Implementation written in SytemVerilog
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Aug 27, 2022 - SystemVerilog
A Framework for Design and Verification of Image Processing Applications using UVM
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Nov 27, 2017 - SystemVerilog
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
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Jan 17, 2018 - Verilog
VIP for AXI Protocol
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May 24, 2022 - SystemVerilog
Universal Virtual Machine for Node and Browser
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Jun 11, 2024 - JavaScript
Generate UVM register model from compiled SystemRDL input
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Jan 25, 2024 - Python
Fun, portable, minimalistic virtual machine.
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Apr 27, 2024 - Rust
DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
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Mar 21, 2024 - SystemVerilog
Control and status register code generator toolchain
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Nov 8, 2023 - Python
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