verilog
Here are 3,818 public repositories matching this topic...
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
-
Updated
Jun 3, 2024 - Verilog
SystemVerilog compiler and language services
-
Updated
Jun 3, 2024 - C++
My technical notes as bite-sized executable programs
-
Updated
Jun 3, 2024 - HTML
HDL libraries and projects
-
Updated
Jun 3, 2024 - Verilog
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
-
Updated
Jun 3, 2024 - Jupyter Notebook
I am trying to develop my skills through daily practice and consistency.
-
Updated
Jun 3, 2024 - Verilog
The repository hosts an ongoing project dedicated to the development of an implementation for the Advanced Encryption Standard (AES) 128-bit block cipher in UART communication. Please be advised that this project is currently in progress and subject to updates.
-
Updated
Jun 3, 2024 - HTML
Open-sourced DDR3 controller
-
Updated
Jun 3, 2024 - Verilog
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
-
Updated
Jun 3, 2024 - JavaScript
Veryl: A Modern Hardware Description Language
-
Updated
Jun 3, 2024 - Rust
a verilog implementation of arbitrary waveform generator with Red Pitaya
-
Updated
Jun 3, 2024 - Jupyter Notebook
Improve this page
Add a description, image, and links to the verilog topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the verilog topic, visit your repo's landing page and select "manage topics."