Prize-2 NTT on FPGA: Supranational Project Fails to Implement on u55n with tool version 2023.2

[threonyl]

Hello,

We have been trying to implement and observe the utilization of the Supranational NTT project on Varium C1100 card. However, after make build we get the following error.

ERROR: [DRC UTLZ-1] Resource utilization: DSPs over-utilized in Pblock pblock_ntt_slr0_x0y3 (This design requires more DSPs cells than are available in Pblock 'pblock_ntt_slr0_x0y3'. This design requires 108 of such cell types but only 96 compatible sites are available in Pblock 'pblock_ntt_slr0_x0y3'. Please consider increasing the span of Pblock 'pblock_ntt_slr0_x0y3' or removing cells from it.)
ERROR: [DRC UTLZ-1] Resource utilization: DSPs over-utilized in Pblock pblock_ntt_slr0_x1y3 (This design requires more DSPs cells than are available in Pblock 'pblock_ntt_slr0_x1y3'. This design requires 108 of such cell types but only 96 compatible sites are available in Pblock 'pblock_ntt_slr0_x1y3'. Please consider increasing the span of Pblock 'pblock_ntt_slr0_x1y3' or removing cells from it.)
INFO: [Vivado_Tcl 4-198] DRC finished with 2 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
212 Infos, 461 Warnings, 5 Critical Warnings and 3 Errors encountered.
place_design failed
place_design: Time (s): cpu = 00:03:40 ; elapsed = 00:01:21 . Memory (MB): peak = 21906.504 ; gain = 0.000 ; free physical = 23457 ; free virtual = 43807
ERROR: [Common 17-39] 'place_design' failed due to earlier errors.

We've observed that the DSP's are placed manually. Is this issue maybe related to the pr.xdc file given?

[threonyl]

For the complete log, see the file below.
runme.log