Discussions

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  DPC-3 mixed traces for multicore

  Hematies asked May 9, 2024 in Q&A · Unanswered

  

  

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  IP of trace instructions

  SteliosKaragiorgis asked Apr 12, 2024 in Q&A · Closed · Answered

  

  

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  Perfect Replacement Policy

  nprzybylski asked Apr 8, 2024 in Q&A · Closed · Unanswered

  

  

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  How to know what the exact instruction looks like？

  Charlie039 started Mar 18, 2024 in General · Closed

  

  

  

  

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  When find_victim return LLC_Ways,it will cause the doule free error

  Cap-jinlonG asked Nov 21, 2023 in Q&A · Closed · Unanswered

  

  

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  Possible error in the default bimodal preditor

  Mingcong-Cao started Mar 18, 2024 in General · Closed

  

  

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  Multi core simulation

  amalrasas asked Mar 18, 2024 in Q&A · Closed · Unanswered

  

  

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  Number of DIB checks per cycle

  0x161e-swei asked Mar 5, 2024 in Q&A · Unanswered

  

  

  

  

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  Branch Prediction Traces

  SteliosKaragiorgis started Feb 28, 2024 in General

  

  

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  About the ship.cc file

  yi-ding-zao-shui asked Mar 7, 2024 in Q&A · Unanswered

  

  

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  Some questions about the results of Champsim

  Charlie039 started Jan 18, 2024 in General

  

  

  

  

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  Cache entry invalidate on hit?

  0x161e-swei asked Feb 27, 2024 in Q&A · Closed · Unanswered

  

  

  

  

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  Are STLB, ITLB and DTLB separate structures in the code?

  Setu-Gupta started Feb 29, 2024 in General

  

  

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  Multicore

  amalrasas asked Feb 13, 2024 in Q&A · Closed · Unanswered

  

  

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  What do all the parameters of CACHE::update_replacement_state means for replacement policies?

  Setu-Gupta asked Feb 13, 2024 in Q&A · Unanswered

  

  

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  Need help with bypassing L1D cache for storing Translation data

  ShreyanshNeekhre started Sep 6, 2023 in General

  

  

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  DEADLOCK in IFETCH_BUFFER?

  ShreyanshNeekhre started Feb 12, 2024 in General

  

  

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  What does the fill_this_level and prefetch_metadata arguments of CACHE::prefetch_line do?

  Setu-Gupta asked Jan 25, 2024 in Q&A · Closed · Answered

  

  

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  Clarification on "virtual_prefetch" config (replacement policy)

  nprzybylski asked Jan 18, 2024 in Q&A · Unanswered

  

  

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  What does the trace name of DPC-3 means?

  yangxin0926 asked Jan 15, 2024 in Q&A · Answered

  

  

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  Is there a way to identify which cache is being initialized in the replacement policy code?

  Setu-Gupta asked Jan 10, 2024 in Q&A · Answered

  

  

  

  

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  Does Champsim model page structure caches?

  arunkp1986 started Oct 10, 2023 in General

  

  

  

  

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  What do the different access_type enum values defined in inc/channel.h represent?

  Setu-Gupta asked Jan 5, 2024 in Q&A · Answered

  

  

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  When I use crc-2 trance, running multi-core trance causes the following bug: Assertion 'packet.address! = 0' failed.how to fix this bug

  Cap-jinlonG asked Dec 19, 2023 in Q&A · Unanswered

  

  

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  Is there a way to have a parameterized replacement policy/branch predictor/prefetcher in ChampSim such that the parameter is passed via the config file?

  Setu-Gupta asked Dec 15, 2023 in Q&A · Answered

  

  

  

  

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