Skip to content
This repository has been archived by the owner on Apr 21, 2021. It is now read-only.

Commit

Permalink
Revert "Merge tag 'v5.10.4' into ASUS-N580GD"
Browse files Browse the repository at this point in the history
This reverts commit 9526474, reversing
changes made to 40132a1.

This is due to version 5.10.4 is not working properly (black screen
while trying to log-in into the system)
  • Loading branch information
Javinator9889 committed Jan 4, 2021
1 parent 2e6624f commit 146be53
Show file tree
Hide file tree
Showing 726 changed files with 3,421 additions and 5,417 deletions.
21 changes: 11 additions & 10 deletions Documentation/locking/seqlock.rst
Expand Up @@ -89,7 +89,7 @@ Read path::

.. _seqcount_locktype_t:

Sequence counters with associated locks (``seqcount_LOCKNAME_t``)
Sequence counters with associated locks (``seqcount_LOCKTYPE_t``)
-----------------------------------------------------------------

As discussed at :ref:`seqcount_t`, sequence count write side critical
Expand All @@ -115,26 +115,27 @@ The following sequence counters with associated locks are defined:
- ``seqcount_mutex_t``
- ``seqcount_ww_mutex_t``

The sequence counter read and write APIs can take either a plain
seqcount_t or any of the seqcount_LOCKNAME_t variants above.
The plain seqcount read and write APIs branch out to the specific
seqcount_LOCKTYPE_t implementation at compile-time. This avoids kernel
API explosion per each new seqcount LOCKTYPE.

Initialization (replace "LOCKNAME" with one of the supported locks)::
Initialization (replace "LOCKTYPE" with one of the supported locks)::

/* dynamic */
seqcount_LOCKNAME_t foo_seqcount;
seqcount_LOCKNAME_init(&foo_seqcount, &lock);
seqcount_LOCKTYPE_t foo_seqcount;
seqcount_LOCKTYPE_init(&foo_seqcount, &lock);

/* static */
static seqcount_LOCKNAME_t foo_seqcount =
SEQCNT_LOCKNAME_ZERO(foo_seqcount, &lock);
static seqcount_LOCKTYPE_t foo_seqcount =
SEQCNT_LOCKTYPE_ZERO(foo_seqcount, &lock);

/* C99 struct init */
struct {
.seq = SEQCNT_LOCKNAME_ZERO(foo.seq, &lock),
.seq = SEQCNT_LOCKTYPE_ZERO(foo.seq, &lock),
} foo;

Write path: same as in :ref:`seqcount_t`, while running from a context
with the associated write serialization lock acquired.
with the associated LOCKTYPE lock acquired.

Read path: same as in :ref:`seqcount_t`.

Expand Down
9 changes: 0 additions & 9 deletions Documentation/x86/topology.rst
Expand Up @@ -41,8 +41,6 @@ Package
Packages contain a number of cores plus shared resources, e.g. DRAM
controller, shared caches etc.

Modern systems may also use the term 'Die' for package.

AMD nomenclature for package is 'Node'.

Package-related topology information in the kernel:
Expand All @@ -55,18 +53,11 @@ Package-related topology information in the kernel:

The number of dies in a package. This information is retrieved via CPUID.

- cpuinfo_x86.cpu_die_id:

The physical ID of the die. This information is retrieved via CPUID.

- cpuinfo_x86.phys_proc_id:

The physical ID of the package. This information is retrieved via CPUID
and deduced from the APIC IDs of the cores in the package.

Modern systems use this value for the socket. There may be multiple
packages within a socket. This value may differ from cpu_die_id.

- cpuinfo_x86.logical_proc_id:

The logical ID of the package. As we do not trust BIOSes to enumerate the
Expand Down
2 changes: 1 addition & 1 deletion Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 5
PATCHLEVEL = 10
SUBLEVEL = 4
SUBLEVEL = 3
EXTRAVERSION =
NAME = Kleptomaniac Octopus

Expand Down
16 changes: 0 additions & 16 deletions arch/Kconfig
Expand Up @@ -143,22 +143,6 @@ config UPROBES
managed by the kernel and kept transparent to the probed
application. )

config HAVE_64BIT_ALIGNED_ACCESS
def_bool 64BIT && !HAVE_EFFICIENT_UNALIGNED_ACCESS
help
Some architectures require 64 bit accesses to be 64 bit
aligned, which also requires structs containing 64 bit values
to be 64 bit aligned too. This includes some 32 bit
architectures which can do 64 bit accesses, as well as 64 bit
architectures without unaligned access.

This symbol should be selected by an architecture if 64 bit
accesses are required to be 64 bit aligned in this way even
though it is not a 64 bit architecture.

See Documentation/unaligned-memory-access.txt for more
information on the topic of unaligned memory accesses.

config HAVE_EFFICIENT_UNALIGNED_ACCESS
bool
help
Expand Down
4 changes: 2 additions & 2 deletions arch/arm/boot/compressed/head.S
Expand Up @@ -116,7 +116,7 @@
/*
* Debug print of the final appended DTB location
*/
.macro dbgadtb, begin, size
.macro dbgadtb, begin, end
#ifdef DEBUG
kputc #'D'
kputc #'T'
Expand All @@ -129,7 +129,7 @@
kputc #'('
kputc #'0'
kputc #'x'
kphex \size, 8 /* Size of appended DTB */
kphex \end, 8 /* End of appended DTB */
kputc #')'
kputc #'\n'
#endif
Expand Down
5 changes: 5 additions & 0 deletions arch/arm/boot/dts/armada-xp-98dx3236.dtsi
Expand Up @@ -266,6 +266,11 @@
reg = <0x11000 0x100>;
};

&i2c1 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11100 0x100>;
};

&mpic {
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
};
Expand Down
5 changes: 5 additions & 0 deletions arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
Expand Up @@ -82,6 +82,11 @@
status = "okay";
};

&vuart {
// VUART Host Console
status = "okay";
};

&uart1 {
// Host Console
status = "okay";
Expand Down
4 changes: 2 additions & 2 deletions arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts
Expand Up @@ -22,9 +22,9 @@
#size-cells = <1>;
ranges;

vga_memory: framebuffer@9f000000 {
vga_memory: framebuffer@7f000000 {
no-map;
reg = <0x9f000000 0x01000000>; /* 16M */
reg = <0x7f000000 0x01000000>;
};
};

Expand Down
2 changes: 1 addition & 1 deletion arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
Expand Up @@ -26,7 +26,7 @@
#size-cells = <1>;
ranges;

flash_memory: region@b8000000 {
flash_memory: region@ba000000 {
no-map;
reg = <0xb8000000 0x4000000>; /* 64M */
};
Expand Down
2 changes: 1 addition & 1 deletion arch/arm/boot/dts/aspeed-g6.dtsi
Expand Up @@ -357,7 +357,7 @@
#gpio-cells = <2>;
gpio-controller;
compatible = "aspeed,ast2600-gpio";
reg = <0x1e780000 0x400>;
reg = <0x1e780000 0x800>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&pinctrl 0 0 208>;
ngpios = <208>;
Expand Down
13 changes: 4 additions & 9 deletions arch/arm/boot/dts/at91-sam9x60ek.dts
Expand Up @@ -569,15 +569,12 @@
atmel,pins = <AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};

usb1 {
pinctrl_usb_default: usb_default {
atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
}; /* pinctrl */

&pmc {
atmel,osc-bypass;
};

&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2 &pinctrl_pwm0_3>;
Expand Down Expand Up @@ -687,8 +684,6 @@
atmel,vbus-gpio = <0
&pioD 15 GPIO_ACTIVE_HIGH
&pioD 16 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
status = "okay";
};

Expand Down
7 changes: 0 additions & 7 deletions arch/arm/boot/dts/at91-sama5d3_xplained.dts
Expand Up @@ -242,11 +242,6 @@
atmel,pins =
<AT91_PIOE 9 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PE9, conflicts with A9 */
};
pinctrl_usb_default: usb_default {
atmel,pins =
<AT91_PIOE 3 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
AT91_PIOE 4 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
};
};
Expand All @@ -264,8 +259,6 @@
&pioE 3 GPIO_ACTIVE_LOW
&pioE 4 GPIO_ACTIVE_LOW
>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
status = "okay";
};

Expand Down
7 changes: 0 additions & 7 deletions arch/arm/boot/dts/at91-sama5d4_xplained.dts
Expand Up @@ -134,11 +134,6 @@
atmel,pins =
<AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
};
pinctrl_usb_default: usb_default {
atmel,pins =
<AT91_PIOE 11 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
AT91_PIOE 14 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
pinctrl_key_gpio: key_gpio_0 {
atmel,pins =
<AT91_PIOE 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
Expand All @@ -164,8 +159,6 @@
&pioE 11 GPIO_ACTIVE_HIGH
&pioE 14 GPIO_ACTIVE_HIGH
>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
status = "okay";
};

Expand Down
19 changes: 8 additions & 11 deletions arch/arm/boot/dts/at91sam9rl.dtsi
Expand Up @@ -282,26 +282,23 @@
atmel,adc-use-res = "highres";

trigger0 {
trigger-name = "external-rising";
trigger-name = "timer-counter-0";
trigger-value = <0x1>;
trigger-external;
};

trigger1 {
trigger-name = "external-falling";
trigger-value = <0x2>;
trigger-external;
trigger-name = "timer-counter-1";
trigger-value = <0x3>;
};

trigger2 {
trigger-name = "external-any";
trigger-value = <0x3>;
trigger-external;
trigger-name = "timer-counter-2";
trigger-value = <0x5>;
};

trigger3 {
trigger-name = "continuous";
trigger-value = <0x6>;
trigger-name = "external";
trigger-value = <0x13>;
trigger-external;
};
};

Expand Down
2 changes: 1 addition & 1 deletion arch/arm/boot/dts/meson8b-odroidc1.dts
Expand Up @@ -224,7 +224,7 @@
reg = <0>;

reset-assert-us = <10000>;
reset-deassert-us = <80000>;
reset-deassert-us = <30000>;
reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;

interrupt-parent = <&gpio_intc>;
Expand Down
2 changes: 1 addition & 1 deletion arch/arm/boot/dts/meson8m2-mxiii-plus.dts
Expand Up @@ -81,7 +81,7 @@
reg = <0>;

reset-assert-us = <10000>;
reset-deassert-us = <80000>;
reset-deassert-us = <30000>;
reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
};
};
Expand Down
2 changes: 1 addition & 1 deletion arch/arm/boot/dts/omap4-panda-es.dts
Expand Up @@ -46,7 +46,7 @@

button_pins: pinmux_button_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x0fc, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */
OMAP4_IOPAD(0x11b, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */
>;
};
};
Expand Down
7 changes: 3 additions & 4 deletions arch/arm/boot/dts/sama5d2.dtsi
Expand Up @@ -656,7 +656,6 @@
clocks = <&pmc PMC_TYPE_PERIPHERAL 51>;
#address-cells = <1>;
#size-cells = <1>;
no-memory-wc;
ranges = <0 0xf8044000 0x1420>;
};

Expand Down Expand Up @@ -725,7 +724,7 @@

can0: can@f8054000 {
compatible = "bosch,m_can";
reg = <0xf8054000 0x4000>, <0x210000 0x1c00>;
reg = <0xf8054000 0x4000>, <0x210000 0x4000>;
reg-names = "m_can", "message_ram";
interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
<64 IRQ_TYPE_LEVEL_HIGH 7>;
Expand Down Expand Up @@ -1131,7 +1130,7 @@

can1: can@fc050000 {
compatible = "bosch,m_can";
reg = <0xfc050000 0x4000>, <0x210000 0x3800>;
reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
reg-names = "m_can", "message_ram";
interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
<65 IRQ_TYPE_LEVEL_HIGH 7>;
Expand All @@ -1141,7 +1140,7 @@
assigned-clocks = <&pmc PMC_TYPE_GCK 57>;
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
assigned-clock-rates = <40000000>;
bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>;
bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>;
status = "disabled";
};

Expand Down
11 changes: 0 additions & 11 deletions arch/arm/boot/dts/tegra20-ventana.dts
Expand Up @@ -3,7 +3,6 @@

#include <dt-bindings/input/input.h>
#include "tegra20.dtsi"
#include "tegra20-cpu-opp.dtsi"

/ {
model = "NVIDIA Tegra20 Ventana evaluation board";
Expand Down Expand Up @@ -593,16 +592,6 @@
#clock-cells = <0>;
};

cpus {
cpu0: cpu@0 {
operating-points-v2 = <&cpu0_opp_table>;
};

cpu@1 {
operating-points-v2 = <&cpu0_opp_table>;
};
};

gpio-keys {
compatible = "gpio-keys";

Expand Down

0 comments on commit 146be53

Please sign in to comment.