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Pull requests: OpenXiangShan/XiangShan

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Pull requests list

L1CacheErrorInfo: code refactor for correct and convenient clockgate refactor Just make code pretty security Some designs may introduce security issues
#3044 opened Jun 5, 2024 by Maxpicca-Li Loading…
StoreQueue: fix bug after refactor commit logic
#3041 opened Jun 5, 2024 by weidingliu Loading…
v0 vl split
#3040 opened Jun 5, 2024 by xiaofeibao-xjtu Loading…
Backend fixtiming: fix rab/exuwb/wbtorob timing do not merge Do not merge this pull request
#3032 opened Jun 3, 2024 by lewislzh Loading…
bpu: use (27, 12, 12) segmented PC in BPU
#3027 opened Jun 1, 2024 by eastonman Loading…
memblock: add rest clockgate of reg. power about power design or optimization
#3017 opened May 28, 2024 by Maxpicca-Li Loading…
Bump huancun: fix dual-core bug
#3013 opened May 27, 2024 by sumailyyc Loading…
ICache: fence.i should flush mainPipe
#3004 opened May 23, 2024 by ngc7331 Loading…
IFU: cut the number of PC registers
#2979 opened May 13, 2024 by my-mayfly Loading…
wpu:fix the issue of abnormal power power about power design or optimization
#2976 opened May 13, 2024 by Maxpicca-Li Loading…
Memblock: Merge memblock timing fixes into master timing Fix bad timing
#2917 opened Apr 24, 2024 by cz4e Loading…
Timing: merge MemBlock timing fixes do not merge Do not merge this pull request
#2857 opened Apr 8, 2024 by good-circle Loading…
Add Sstval support do not merge Do not merge this pull request
#2850 opened Apr 8, 2024 by chenguokai Loading…
Add the mill wrapper (millw)
#2846 opened Apr 4, 2024 by Flowdalic Loading…
bpu: gate s0 registers when s0_stall
#2791 opened Mar 15, 2024 by eastonman Loading…
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