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AutoSA: Polyhedral-Based Systolic Array Compiler
C++ 185 31
TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerators.
C++ 143 27
[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
C++ 115 26
[FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
Python 110 18
C++ 63 17
Stencil with Optimized Dataflow Architecture Compiler
Python 16 5
Use a customized RTL testbench for cosim, avoid generating .xclbin
Serpens is an HBM FPGA accelerator for SpMV
A flexible package manager that supports multiple versions, configurations, platforms, and compilers.
Stencil with Optimized Dataflow Architecture
ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS
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