Lots of small improvements

• Added a search function
• Added a presentation mode.
• Adds Q and CTRL-Q hotkeys to copy the component the mouse
  pointer is hovering over.
• Now there is resetRandom method available in the test code to
  reset the random number generator used by the random function.
• The remote server is now disabled by default.
  It must be enabled in the settings.
• When a new component has been placed with CRTL click,
  you can place another one.
• Fixes the ignored default value in demuxer HDL export.

Some minor improvements and bug fixes

• Allows loading byte base files in big-endian format.
• Added some more DIL chips
• Tunnel now shows signal state
• Fixes tutorial dialog positioning issue
• Fixed some issues with 7489 and 74189
• Fixed a bug in the LUT component that caused difficulties
  when generic code was executed.
• Fixed an issue in the seven segment persistence of vision
  implementation.
• Fixed a Verilog generation issue when using filenames that
  contain spaces.

Lots of small improvements

• Inputs and outputs can have a smaller shape.
• Added paste functionality to ROM data editor.
• Added an rle encoding for storing rom content, which can
  result in smaller dig files.
• Added some more ATF150x devices
• Probe is able to count edges.
• Italian translation was added, special thanks to Luca Cavallari
• Added an external component that is based on a file instead
  of storing the code in the component itself.
• Fixed an issue with clicking on tightly placed components.
• Allows variable sample size in default data graph.
• Added an option to skip certain sub-circuits in HDL creation.
  This allows the user to use a handwritten HDL implementation
  of the sub-circuit.

v0.27: Added fixed point and floating point number formats

- Added fixed point and floating point number formats.
- Adds a dialog to create a behavioral fixture.
- Added a CSV truth table export and import.
- Added a search field to the component tree view.
- Added 74299
- Refactoring of the expression format setting.
  CAUTION: All the general settings are maybe lost at restart!
  To avoid this, open the .digital.cfg file and remove the <entry>
  containing the <string>ExpressionFormat</string> if it's present.

v0.26.1: Bug Fixes

- fixes a bug bug that prevents a short from being detected
  when no component is involved.
- fixes an issue in the importer of logisim hex files.

v0.26: Improved testing of processors

- Performance improvement of the simulation start.
- Improved the gui to modify the k-map layout.
- Improved testing of processors.
- Improved the layout of fsm transitions in the fsm editor.
- Added French translation. Special thanks to Nicolas Maltais who
  provided the translation.
- Added a "Not Connected" component to output a constant high-z value.
- If a high-z value is connected to a logic gate input, the read value
  is undefined.
- Improved debugging: It is possible to set the circuit to the
  state of a certain test result, by simply clicking on it.
- Generic circuits are easier to debug: It is possible now to create
  a specific, concrete circuit from a generic one.
- In generic circuits it is now possible to add components and
  wires to the circuit programmatically.
- It is now possible to use a probe as output in a test case.
- Adds undo to text fields
- If IEEE shapes are selected in the settings, also the CircuitBuilder
  uses wide shapes in the created circuits.
- Fixed a bug in the Demuxer Verilog template that causes problems
  when using multiple demuxers in the same circuit.
- Fixed a bug in the value editor, which occurs, if high-z is the
  default value of an input.
- Fixed an issue which avoids to restart a running simulation by just
  click on the start button again.
- Added IC 74190 to the Library.

v0.25: Support for color-blind users and many other small improvements.

- Color schemes have been added to support color-blind users.
- Unipolar and bipolar stepper motors were added.
- Moved the "lib" folder from the "examples" folder to the root folder.
  - In case you have added your own library circuits, you have to move
    them manually as well.
- Reordering of the cells in the K-Map.
- Counters are able to act as program counters via the remote interface.
- The circuits created have a more visible separation of the inputs.
- The hex seven seg display is switched off in case of a high-z input.
- A Stop component was added.
- Improved test case parser. Now the test case is able to react on the
  circuit's state.
- 7482, 74193 and 744017 were added
- Breaking changes:
  - The layout shape uses a slightly different algorithm to determine
    the pin positions. You may need to adjust usages of embedded circuits
    that use the layout shape.
  - The CommandLineTester has moved! Tests are now executed like this:
    java -cp Digital.jar CLI test [file to test]
       [-tests [optional file with test cases]]
  - Text formatting was reworked. Disable formatting with a '\' in the
    beginning does not longer work. Use "\_" to escape a underscore.

v0.24: Lots of small improvements

- Improved SVG export
- Allows to disable inputs and outputs in the measurement graph.
- Model analyzer is able to use switches as inputs.
- Editor is able to store views ([CRTL]+[[n]] to create, [[n]] to recall
  a view. So [CTRL]+[1] stores a view in slot one and [1] recalls it.
- The octal number format was added.
- A mirroring option was added to some components.
- Custom Java implemented components can now also implement HDL code to
  represent the component in an HDL export.
- Added a undo function to the table editor.
- Adds a command line interface for testing circuits.
- Allows to disable "snap to grid" in text and rectangle components.
- A push button combined with a LED was added.
- A VGA monitor was added.
- Improved naming of new Tunnels. Unnamed Tunnels are ignored silently.
- Overlapping pins are now connected.
- Added support for INOUT ports in HDL generation.
- Fixed an issue with Chinese text rendering.

v0.23: Added generic circuits and simplified the integration of FPGA boards.

- Added generic circuits. Now it is possible to parameterize a sub circuit.
  Allows e.g. the creation of a barrel-shifter with selectable bit width.
- Circuit analyser is now able to analyse the built-in counters.
- Simplified the integration of FPGA boards.
  Board integration is now possible without creating Java code or
  even recompiling. See the BASYS3.config in examples/hdl as an example.
- Improved the label creation in the model analyzer.
- Improved performance of the boolean equation minimizer.
- Hex reader/writer supports RLE encoding like Logisim does.
- Added Spanish translation. Special thanks to Ángel Millán who provided
  the translation.
- Added a simple interactive beginners tutorial.
- Added a statistics dialog which shows the number of used components.
- Added scrollbars.
- Multiple break components are allowed.
- The fsm dialog loads the correct fsm if a circuit is open which
  is based on that fsm.
- If a VHDL defined component is used, ghdl now uses VHDL-2008.
- Added "Warren’s Crazy Small CPU" designed by Warren Toomey as a
  74xx circuit example.
- Fixed an issue in the "RAM, Chip select" component which was not fully
  asynchronous.
- Fixed swapped IC numbers 7447 and 7448.

v0.22: Many small improvements.

- Improved the RAM/ROM data loader. Now binary files and Intel HEX files
  are supported.
- Added a RAM that can be synthesized on an FPGA using block RAM.
- Now its possible to create circuits using lookup tables.
- More consistent handling of the initial state in the FSM editor.
- Added a rectangle to visually group elements.
- Added a MIDI component.
- The line number and the context from the test case description is shown
  in test result table.
- Added Portuguese translation. Special thanks to Theldo Cruz Franqueira
  who provided the translation.
- Breaking changes:
  - The timing of the EEPROM with a single data port has changed.
    See help text for details.
  - The timing of the RAM with Chip Select has changed.
    See help text for details.