Benchmark Circuits

This repository contains a set of benchmark circuits collected from two sources: ISCAS85 Benchmarks and the EPFL Combinational Benchmark Suite

These circuits have been synthesized with Cadence Genus. The primary purpose of this repository is to maintain consistent formating between the two sources. Specifically each circuit is in the generic gate verilog format and the circuit top and filename matches.

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
Priority.v		Priority.v
README.md		README.md
adder.v		adder.v
arbiter.v		arbiter.v
bar.v		bar.v
c1355.v		c1355.v
c17.v		c17.v
c1908.v		c1908.v
c2670.v		c2670.v
c3540.v		c3540.v
c432.v		c432.v
c499.v		c499.v
c5315.v		c5315.v
c6288.v		c6288.v
c7552.v		c7552.v
c880.v		c880.v
cavlc.v		cavlc.v
ctrl.v		ctrl.v
dec.v		dec.v
div.v		div.v
i2c.v		i2c.v
int2float.v		int2float.v
log2.v		log2.v
max.v		max.v
memctrl.v		memctrl.v
multiplier.v		multiplier.v
router.v		router.v
sin.v		sin.v
sqrt.v		sqrt.v
square.v		square.v
voter.v		voter.v

jpsety/verilog_benchmark_circuits

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