-
Siemens
- Netherlands
- https://www.linkedin.com/in/ozlemaltinay
Block or Report
Block or report oaltinay
Contact GitHub support about this user’s behavior. Learn more about reporting abuse.
Report abusePinned
-
riscv-gcc
riscv-gcc PublicForked from sifive/riscv-gcc
Fork to add RISC-V specific GCC built-in functions and machine descriptions for extended instructions for ASCON cryptography algorithm.
C
-
riscv-isa-sim
riscv-isa-sim PublicForked from riscv-software-src/riscv-isa-sim
Fork to add extended RISC-V instructions to Spike, a RISC-V ISA Simulator, for ASCON cryptography algorithm. Counts clock cycles of the new instructions and simulates for a RISC-V processor.
C
-
riscv-binutils-gdb
riscv-binutils-gdb PublicForked from sifive/riscv-binutils-gdb
Fork to add RISC-V extended instructions for ASCON cryptography algorithm.
C
-
If the problem persists, check the GitHub status page or contact support.