"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

All my projects, homework, hand writings, course slides and anything I have learned and done during my study in IUT university😊. feel free to give it a ⭐=)

CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] <Semester III>

Final Project for Digital Systems Design Course, Fall 2020

My activity in digital systems

Implementation and verification of a hardware-based controller for a three-phase induction motor on an FPGA — Bachelor's Thesis [UPC-TTU, 2019]

Digital Systems Design - Spring 2023 - Sharif University of Technology

Term project and lab assignments for CS303 - Logic and Digital System course in Sabancı University, Fall 2021-2022.

Repositorio con las 12 prácticas en VHDL para el curso impartido por la profesora Nayeli Vega, tomada en la ESCOM, IPN.

This repository contains projects developed by students of the Bachelor of Computer Engineering program at Qazvin Islamic Azad University (QIAU). The projects cover various topics in computer engineering, including digital systems, microprocessor, logical circuits, computer graphics, and etc.

Digital Logic Design (DLD) is a fundamental subject for the engineering students worldwide. Well, many students find it difficult to design the digital circuits properly while pursuing the DLD course in colleges or universities. Therefore, I will try to assist those students by sharing my lab works with them.

Lab projects using Verilog HDL

3-stage RISC-V Pipelined Processor with interrupt CSR support

Single Cycle Processor written in SystemVerilog for executing machine code of RISC-V ISA

Contains my resume

👾 My studies with Verilog and notions of digital systems.

Binary Adder, Subtractor, Multiplier, Divider in VHDL with FPGA board.

Implementation of a low-pass FIR filter in Verilog HDL.

Advanced Pheripheral Bus design using verilog HDL

Digital System Design Course (1st year, 2nd Semester)