Deep learning toolkit-enabled VLSI placement

A High-performance Timing Analysis Tool for VLSI Systems

Standard Cell Library based Memory Compiler using FF/Latch cells

Dr. CU, VLSI Detailed Routing Tool Developed by CUHK

A Standalone Structural Verilog Parser

VLSI EDA Global Router

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

DATC RDF

Courseworks of CS6165 VLSI Physical Design Automation, NTHU.

Coriolis VLSI EDA Tool (LIP6)

Steiner Shallow-Light Tree for VLSI Routing

Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII Flow is implemented with Openlane using Skywater130nm PDK. Custom-designed standard cells with Sky130 PDK are also used in the flow. Timing Optimisa…

This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK

Some simple examples for the Magic VLSI physical chip layout tool.

A LEF/DEF Utility.

Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.

5 Day TCL begginer to advanced training workshop by VSD

This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130

VLSI CAD Algorithm Visualizations implemented as Java Applications